Data communication is a critical function of many electronic devices, and integrated circuits are typically an integral part of a data transmission scheme. Data is typically transmitted at a variety of levels, such as between elements of an integrated circuit, between integrated circuits on a circuit board, between circuit boards, or between systems, which could be local or remote. Data can also be transmitted as a serial data stream or in parallel data streams. Transferring data by way of a serial data stream makes efficient use of the available resources, such as the number of input/output pins used to transfer data. However, the transmission of data in any data transmission scheme must not only be reliable, but must also be usable when received at a destination.
Accordingly, data is often transferred according to predefined protocols. For example, the Medium Access Control (MAC) protocol defined by the I.E.E.E. 802.03 standard establishes the data link layer for the telecommunications and information exchange between local and metropolitan area networks. The I.E.E.E. 802.03 MAC protocol could be used to provide the data link layer of an Ethernet LAN system, for example. The relationship of the data link layer to other layers of the I.E.E.E. 802.03 standard is shown in FIG. 1. The MAC protocol generally encapsulates payload data by adding a header (Protocol Control Information (PCI)) before the data and appending a Cyclic Redundancy Check (CRC) after the data. The entire frame is preceded by a small idle period and a preamble. However, the circuitry required to implement various data transfer protocols is typically different. Even within a given protocol, data could be transferred at different rates, and could require different circuitry.
While various types of integrated circuits provide different levels of flexibility in implementing circuits, one class of integrated circuits which provides particular flexibility in implementing circuits is a programmable logic device (PLD), such as a field programmable gate array (FPGA). While a programmable logic device provides a number of programmable functions, as will be described in more detail in reference to FIG. 11, a programmable logic device could also provide other features which are provided in fixed hardware, and therefore are non-programmable. For example, the programmable logic device could include one or more data transceivers, such as multi-gigabyte data transceivers. Although the programmable logic portions provide flexibility to the user, the user may be restricted by a fixed portion of a programmable logic device. For example, a programmable logic device having a high speed data transceiver is limited to a data protocol for that transceiver to transmit the data. That is, the user may be required to transmit only a single stream of data at a given data rate.
Further, the needs of a user for transmitting data in an integrated circuit may vary. A user may need to transmit data at multiple data rates. For example, it is very common that numerous Ethernet MAC cores are required for debugging and communicating with embedded processors; implementing an Ethernet switcher/router application; providing chip to chip or backplane interfaces, etc. However, in order to transmit the various data streams at different data rates, multiple data transceivers would be required. As shown for example in FIG. 2, each of a plurality of data streams 202 would have a data control circuit 204 which receives data from a FIFO 206 and outputs the data to a FIFO 208 and a media independent interface (MII) 210, as is well known in the art. Each data control circuit would require a data link layer according to a protocol, such as a MAC protocol defined by I.E.E.E. 802.03. That is, the data link layer provided according to the MAC protocol would have to be duplicated, in programmable logic of a programmable logic device, for example, for each of the data streams received by the data transceivers or by general I/O ports.
While circuit designers are always working to reduce the area occupied by circuits of a given design to either reduce the size of the integrated circuit or increase the circuit capacity of a given integrated circuit, implementing multiple data link layers requires considerable space on the integrated circuit, as well as increases the noise on the integrated circuit. Also, a given integrated circuit may have a data link layer which has a certain data rate and an overall throughput. That is, an integrated circuit may implement a high speed data protocol which has the capacity to transmit a certain amount of data at a high rate, but would be unable to transfer the same amount of data as a plurality of data streams at a lower data rate to achieve the same overall throughput. For example, a conventional 1 Gigabits per second (Gbps) MAC core would not be able to transmit 10 streams of data at 100 Megabits per second (Mbps).
Accordingly, there is a need for a method of and circuit for generating a plurality of serial data streams employing a single data control circuit.